Gate Sizing Minimizing Delay and Power/Area
نویسندگان
چکیده
In this work we present a gate sizing tool based on Geometric Programming. The optimization can be done targeting both, delay and power/area minimization. In order to qualify our approach, the ISCAS’85 benchmark circuits are mapped for 350nm and 45nm technologies using typical standard cell libraries. Next, the mapped circuit is sized using our tool and the result is comparated to the original mapped circuit. The speed is increased by 21% and 4.5%, on average, for 45nm and 350nm technology, respectively, keeping the same area and power values of the sizing provided by standard-cells library. For power/area optimization, where the delay was restricted to the delay value found at delay minimization, the reduction was 28.2% in area and 27.3% in power consumption, on average, considering 45nm technology and 29.9% in area and 28.5% in power, on average, considering 350nm technology.
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